Re-Architecting DRAM Memory Systems with 3D Integration and Photonic Interfaces

In recent years, due to well-known “memory-wall” limitations, DRAM latency and energy/bit characteristics have not improved as rapidly as DRAM capacity and bandwidth with technology scaling. Despite plenty of research efforts during the last decade to overcome the hurdles in DRAM scaling, high performance computing systems of the future will still require improvements in DRAM latency and bandwidth within stringent power constraints. In this paper, firstly we establish the need for reinventing DRAM architectures by identifying the limiting features of several state-of-the-art DRAM architectures. Then we discuss some useful features of 3D integration and photonic interfaces that have the potential to greatly improve the performance and energy of future DRAMs. Finally, we present a novel optically-interfaced 3D-DRAM architecture with 3D data organization, which achieves 4.4× improvement in performance and 83.8% reduction in per-bit energy on average over 3D-DRAM architectures from prior work.